----------------------------------------------------------------------
-- Bit-serial subtraction unit
-- Stephen West, James Carroll
-- BYU ECEn 620, October 2008
--
-- Computes the difference of two, one-bit signals, which come in 
-- bit-serially
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	-- latency 0 clk
entity BitSerialSub is
	generic(
		word_length:integer:=8;
		code_vector_length:integer:=16;
		system_word_length:integer:=12
	);
	port(
		clk, a_in, b_in, lsb_in:in std_logic;
			sub_out, lsb_out: out std_logic
	);
end entity;

architecture BitSerialSub of BitSerialSub is
	component FullAdder is
		port(
			a_in, b_in, c_in:in std_logic;
				add_out, c_out: out std_logic
		);
	end component;
	signal carry_reg, b_n, c_in, c_out: std_logic:='0';
begin
	-- a-b = a+(not b +1)
	--a+~b+(c|lsb)
	--register the carry
	b_n <= not b_in;
	c_in<=carry_reg or lsb_in;
	add1: FullAdder port map(c_out=>c_out,c_in=>c_in, a_in=>a_in, b_in=>b_n, add_out=>sub_out);
	--assert (carry_reg and lsb_in)='0' report "not (c and lsb) -- to few bits" severity failure;
	process(clk, c_out)
	begin
		if(clk'event and clk='1') then
			carry_reg<= c_out;
		end if;
	end process;
	lsb_out<=lsb_in;
end architecture;
